NEC PD17062 Manual do Utilizador descarregar pdf (Página 219)

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PD17062

18. PLL FREQUENCY SYNTHESIZER

18.1 PLL FREQUENCY SYNTHESIZER CONFIGURATION

Fig. 18-1 is a block diagram of the PLL frequency synthesizer.

As shown in Fig. 18-1, the PLL frequency synthesizer consists of a programmable divider (PD), phase

comparator (

-DET), reference frequency generator (RFG), and charge pump. Strictly speaking, a PLL

frequency synthesizer is configured by connecting these blocks with an external lowpass filter (LPF) and

voltage-controlled oscillator (VCO).

See Sections 18.3 to 18.5 for details of these blocks.

Fig. 18-1 PLL Frequency Synthesizer Block Diagram

Note External circuit

VCO PSC EO

Unlock detection

block

Programmable

divider (PD)

Phase

comparator

( -DET)

Charge pump

Reference frequency

generator (RFG)

Prescaler

PB595

Note

Voltage-controlled

oscillator (VCO)

Lowpass filter

(LPF)

Note

1 2 ... 214 215 216 217 218 219 220 221 222 223 224 ... 295 296

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