NEC PD17062 Manual do Utilizador descarregar pdf (Página 230)

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PD17062

(2) PLL unlock FF delay control register (PLULSEN)

When the unlock FF disable mode is selected, the unlock FF remains set. So, note that if the PLL unlock

FF judge register checks the unlock FF in the unlock FF disable mode, it always appears to be unlocked

(PLLUL flag = 1).

Fig. 18-8 Configuration and Functions of the PLL Unlock FF Delay Control Register (PLULSEN)

Flag symbol

3 b2 b1 b0

32H R/W

Address Read/write

Upon reset

Power-on

Clock stop

1.25-1.5 s or more

3.5-3.75

s or more

0.25-0.5

or more

Unlock FF disabled (Always to be set)

Hold

Sets the delay time between the reference (fr) and division frequency (fN) signals,

which is necessary to set the unlock FF.

Fixed to 0.

PLL unlock FF

delay control

(PLULSEN)

Hold

1 2 ... 225 226 227 228 229 230 231 232 233 234 235 ... 295 296

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