NEC PD17062 Manual do Utilizador descarregar pdf (Página 96)

100

101

PD17062

Example 2. GET instruction

When the 8-bit data of a peripheral register is read, the value of the eight high-order bits (DBF3 and DBF2)

of the data register does not change.

Of the 8-bit data of the data register, each bit that is not a valid peripheral register bit becomes 0 or

unpredictable. Whether the bit becomes 0 or unpredictable is decided in advance for each peripheral register.

10.4.3 State at Peripheral Register Reset

The valid bits of each peripheral register are reset as follows:

DBF3 DBF2 DBF1 DBF0

15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Peripheral register

7 b6 b5 b4 b3 b2 b1 b0

GET

Data buffer

Don't careDon't care

0 or unpredictable

The value of the

peripheral register

is read without alteration.

Valid bits

Reset Valid bit state

Power-on Unpredictable

Clock-stop Previous state held

CE Previous state held

1 2 ... 91 92 93 94 95 96 97 98 99 100 101 ... 295 296

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