Nec Network Controller uPD98502 Manual do Utilizador descarregar pdf (Página 170)

100

101

CHAPTER 2 V

4120A

170

Preliminary User’s Manual S15543EJ1V0UM

Figure 2-67. Instruction Cache Line Format

22 21

PTag

Data

PTag : Physical tag (bits 31 to 10 of physical address)

V: Valid bit

Data : Cache data

2.7.2.2 Organization of the data cache (D-cache)

Each line of D-cache data has an associated 25-bit tag that contains a 22-bit physical address, a Valid bit, a Dirty

bit, and a Write-back bit.

The V

4120A Core D-cache has the following characteristics :

 write-back

 direct-mapped

 indexed with a virtual address

 checked with a physical tag

 organized with a 4-word (16-byte) cache line.

Figure 2-68 shows the format of a 4-word (16-byte) D-cache line.

Figure 2-68. Data Cache Line Format

WV D PTag

Data

24 23 22

063

111

W : Write-back bit (set if cache line has been written)

D: Dirty bit

V: Valid bit

PTag : Physical tag (bits 31 to 10 of physical address)

Data : D-cache data

1 2 ... 165 166 167 168 169 170 171 172 173 174 175 ... 594 595

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