Nec Network Controller uPD98502 Manual do Utilizador Página 454

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APPENDIX A MIPS III INSTRUCTION SET DETAILS
454
Preliminary Users Manual S15543EJ1V0UM
BGTZ
Branch On Greater Than Zero
BGTZ
rs
BGTZ
0 0 0 1 1 1
0
0 0 0 0 0
offset
31 26 25 21 20 16 15 0
655 16
Format:
BGTZ rs, offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit
offset
, shifted left two bits and sign-extended. If the contents of general register
rs
are zero or greater when
compared to zero, then the program branches to the target address, with a delay of one instruction.
Operation:
32 T:
target (offset
15
)
14
|| offset || 0
2
condition (GPR [rs]
31
= 0) and (GPR [rs] 0
32
)
T+1: if condition then
PC PC + target
endif
64 T:
target (offset
15
)
46
|| offset || 0
2
condition (GPR [rs]
63
= 0) and (GPR [rs] 0
64
)
T+1: if condition then
PC PC + target
endif
Exceptions:
None
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