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101

CHAPTER 2 V

4120A

172

Preliminary User’s Manual S15543EJ1V0UM

2.7.3.1 Cache write policy

The V

4120A Core manages its data cache by using a write-back policy; that is, it stores write data into the cache,

instead of writing it directly to memory

Note

. Some time later this data is independently written into memory. In the

4120A implementation, a modified cache line is not written back to memory until the cache line is to be replaced

either in the course of satisfying a cache miss, or during the execution of a write-back CACHE instruction.

When the CPU core writes a cache line back to memory, it does not ordinarily retain a copy of the cache line, and

the state of the cache line is changed to invalid.

Note Contrary to the write-back, the write-through cache policy stores write data into the memory and cache

simultaneously.

2.7.4 Cache states

(1) Cache line

The three terms below are used to describe the state of a cache line:

 Dirty: a cache line containing data that has changed since it was loaded from memory.

 Clean: a cache line that contains data that has not changed since it was loaded from memory.

 Invalid: a cache line that does not contain valid information must be marked invalid, and cannot be used.

For example, after a Soft Reset, software sets all cache lines to invalid. A cache line in any other

state than invalid is assumed to contain valid information. Neither Cold reset nor Soft reset makes

the cache state invalid. Software makes the cache state invalid.

(2) Data cache

The data cache supports three cache states:

 Invalid

 Valid clean

 Valid dirty

(3) Instruction cache

The instruction cache supports two cache states:

 Invalid

 Valid

The state of a valid cache line may be modified when the processor executes a CACHE operation. CACHE

operations are described in APPENDIX A MIPS III INSTRUCTION SET DETAILS.

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